1. Field of the Invention
The present application relates to high-speed communication interfaces, including high-speed parallel bus interfaces for integrated circuits; and more particularly to calibration of such interfaces.
2. Description of Related Art
High-performance data processing applications are driving the demand for data rates past the GigaHertz range. As processor clock speeds increase to meet the demand, high-performance parallel bus interface technology is being developed to meet these needs. In parallel bus interfaces, a number of serial lines are operated in parallel. So-called SERDES (short for serializer-deserializer) technologies are being applied for each of the parallel lines. Other high-performance bus interface technologies are provided by Rambus, Inc., including products provided under the tradenames XDR™ High Performance Memory Interface Technology, Raser™ High Performance Interface Technology, and Redwood™ High Performance Parallel Bus Interface Technology. Background concerning high speed interfaces is found in U.S. Pat. No. 6,396,329 B1, entitled Method and Apparatus for Receiving High Speed Signals with Low Latency; and in U.S. Pat. No. 6,473,439, entitled Method and Apparatus for Fail-Safe Resynchronization with Minimum Latency.
One problem which becomes more important as communication speeds increase is calibration of clocks and sample timing. The optimal sampling point for each bit of data is controlled by many independent variables, which can be boiled down to a simple relationship between clock and data. There is an optimal singular sampling point for all data patterns at any given moment. Complicating matters are changes to the optimal sampling point. High-frequency noise, known as jitter, places a cloud of uncertainty around this optimal sampling point. Methods to compensate for jitter have been limited in effectiveness. Thus, systems with very low jitter are preferred. Low-frequency noise, known as skew, comprises slowly changing offsets in the optimal sampling point, for which compensation can be provided, depending on the system's ability to track of these sources of error.
Several methods have been developed to track and calibrate the sources of error that cause skew. One method is known as oversampling. Oversampling requires sampling the data more than once per bit time and coding the data for guaranteed transitions. These oversampling approaches involve clock/data recovery schemes that use clock/data patterns such as 8b/10b, and the like. Most current SERDES technologies use the 8a/10b coding scheme. This approach has the advantage that it relies on the same number of physical channels as logical channels for the communication link. However, there is an inherent 25% bandwidth penalty built-in the 8b/10b coding scheme. Also, the oversampling requires increased power consumption.
Another method for tracking and calibrating sources of error of involves performing an initial calibration, and then letting the system run open loop. This process requires good circuits to track all temperature-related drift components. One well-known example of this approach is known as the source synchronous technique. A timing reference is sent, typically on an independent physical channel, along with the data to compensate for drift between clock and data. The tracking time constant needs to be as fast as possible, with minimum time lag. Additionally, a single offset value would be optimal for all operating conditions on each of the lines in the parallel bus. If good tracking can be achieved across all drift conditions on all of the lines in the parallel bus, a source synchronous approach is quite compelling.
In another approach, where tracking times are not optimal, each link can be temporarily disabled and used for a fast periodic calibration. This type of periodic calibration requires precise logical synchronization between transmit and receive operations to perform the calibration efficiently during a calibration window, without jeopardizing real data in the process. Although synchronized periodic operations may be possible in a master-slave implementation, peer-to-peer periodic operations may be too prohibitive to be efficiently incorporated.
Selecting an optimal chip-to-chip interconnect strategy relies not only on the traditional metrics of latency and effective bandwidth, but also the area and power required to do so. System solutions that provide superior area/bandwidth and power/bandwidth trade-offs, while still meeting the bandwidth and latency requirements of system designers, are required to continue to scale performance in line with expected trends.